1. Field of the Invention
The present invention relates to a semiconductor apparatus and a clock generation unit.
2. Description of Related Art
A semiconductor apparatus that has a circuit to generate a clock for testing an internal circuit of the semiconductor apparatus is described in Japanese Unexamined Patent Publication No. 6-242188 (Kitaguchi et al.) in FIGS. 1 and 2, paragraphs 0020 and 0029 to 0036. This semiconductor apparatus has an Exclusive-OR gate that generates a clock signal at a higher frequency than a plurality of input test clocks based on a phase difference of these test clocks and outputs it to the internal circuit. This semiconductor apparatus allows testing at a higher clock speed than the actual operation of the semiconductor apparatus even with an IC tester.
A tester is used to test a semiconductor apparatus. However, there is a limit to a clock speed which a tester can supply, and it has been unable for a tester to supply a clock of a higher speed than the actual operation speed of a semiconductor apparatus. Kitaguchi et al. teaches a technique for such a tester. The technique supplies two clocks with different phases from a tester. Using a phase difference between the two clocks, it supplies a clock at a higher frequency than a clock that is generated by the tester to an internal circuit of a semiconductor apparatus.
However, the technique taught by Kitaguchi et al. can supply a clock at a frequency that is only up to double the frequency of a clock supplied from the tester. It thus fails to supply a high speed clock that is used for scan test or the like.
It is possible to supply a clock at a frequency of N times higher than a clock frequency supplied from a tester as a clock for operating test to an internal circuit by placing a N-multiply PLL (N>2) in a semiconductor apparatus allows. However, since the multiply PLL generally occupies a large area, it causes an increase in the costs of a semiconductor apparatus.